Czy chodzi o coś takiego ??
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity lcd_dek is port (
din: in std_logic_vector(3 downto 0);
clk: in std_logic;
bp: inout std_logic;
segm_o: out std_logic_vector(6 downto 0)
);
end lcd_dek;
architecture ar_dyn of lcd_dek is
signal segm: std_logic_vector(6 downto 0);
begin
with din select
-- gfedcba
segm <= "0111111" when "0000", -- 0
"0000110" when "0001", -- 1
"1011011" when "0010", -- 2
"1001111" when "0011", -- 3
"1100110" when "0100", -- 4
"1101101" when "0101", -- 5
"1111101" when "0110", -- 6
"0000111" when "0111", -- 7
"1111111" when "1000", -- 8
"1101111" when "1001", -- 9
"0000000" when others; --
wygaszenie
segm_o(0) <= segm(0) xor bp;
segm_o(1) <= segm(1) xor bp;
segm_o(2) <= segm(2) xor bp;
segm_o(3) <= segm(3) xor bp;
segm_o(4) <= segm(4) xor bp;
segm_o(5) <= segm(5) xor bp;
segm_o(6) <= segm(6) xor bp;
bp <= clk;
end ar_dyn